Digital System Research

Archive for Latest Developments

DSR to unveil its RNS-TPU and error correcting arithmetic at SC19

March 8, 2019 –  Come see Digital System Research at SC19!  This year, SC19:  The International Conference for High Performance Computing, Networking, Storage and Analysis will be held in Denver Colorado at the Colorado Convention Center on November 18-21, 2019.  DSR will unveil its TPU-ec prototype, the worlds first tensor processing unit which supports error […]

DSR announces space-based TPU

January 21, 2019 –  Digital System Research, Inc is proud to announce it’s EC series TPU processor targeting high-speed matrix and AI applications requiring extreme high reliability.  The TPU-EC series processor achieves extreme reliability by providing continuous error-corrected matrix multiplication and vector arithmetic.  DSR’s new processor is suitable for artificial intelligence applications, or general purpose […]

DSR posts comparison of Modular computation versus Quantum computation

April 11, 2018 –  DSR has posted an interesting comparison of the benefits of Modular computation versus Quantum computation.  The fact that Modular Computation is a new form of digital arithmetic is important, since it means we can program and process conventional arithmetic algorithms using it.  For Quantum computers, unfortunately the same cannot be said.  […]

DSR to deliver presentation at ISCAS 2018

February 17, 2018 – Join us at ISCAS !  DSR will present its RNS TPU at the International Symposium on Circuits and Systems 2018 (ISCAS 2018) and will be providing a short presentation of the huge performance gains that are possible in the emerging field of modular computation, especially as it pertains to matrix multiplication […]

DSR assembles team for development of High Precision TPU accelerator

June 20, 2017 – DSR announces its has assembled a team to pursue the development of a wide precision TPU accelerator card.  Eric Olsen, president of DSR states “It has become evident that support of hardware based matrix multiplication is a key element in many neural network acceleration chips, such as Google’s TPU chip and […]

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