Digital System Research

DSR assembles team for development of High Precision TPU accelerator

June 20, 2017 – DSR announces its has assembled a team to pursue the development of a wide precision TPU accelerator card.  Eric Olsen, president of DSR states “It has become evident that support of hardware based matrix multiplication is a key element in many neural network acceleration chips, such as Google’s TPU chip and Nvidia’s Volta GPU.  DSR will use hardware based matrix multipliers to process neural network applications using the residue number system (RNS), as this architecture significantly reduces the overhead of conversion.  Once data is converted, we can take advantage of RNS fractional product summation, which is carry free, and far more efficient and much faster than binary methods.”  DSR is seeking to develop key methods and original IP during the project, which should take about 18 months.  The project will make use of high-end FPGA devices on commercially available PCIe cards.  Eric further states: “We welcome major processor companies to collaborate with us in this exciting endeavor.  The fact is our methods are empowered by the underlying mathematics, and not the process technology or architecture.  There is no way our competitors can circumvent this using classical binary methods. However, leading edge process technology is ultimately needed to take full advantage of this new approach.”  DSR is a Nevada corporation engaged in the development and design of RNS based processors.

Leave a Reply

Your email address will not be published. Required fields are marked *

Delivering the next leap in computation™