Digital System Research


Rez-9 Architecture

  • First RNS based co-processor for general purpose processing!
  • Performs both wide word integer and fixed point fractional math!
  • Operates as a co-processor to the Altera NIOS-II soft CPU
  • Develop RNS software algorithms using Altera NIOS software development tools!
  • IP currently targets -IV series Altera FPGAs
  • Rez-9A now in beta test, target release 2nd quarter 2015

Rez9 Family Features and Benefits

  • Dual ALU design with 1024 word dual ported register file.
  • Single clock add, subtract and multiply of very long word integers.
  • Single clock add, subtract and integer multiplication of fixed point fractional formats.
  • 32.32 and 64.64 bit equivalent fixed point multiplier.
  • Long word integer divide and 32.32 fixed point divide.
  • Advanced product sum and MAC instruction set extensions.
  • High-speed RNS fixed point format conversion to binary double floating point.
  • Various hardware configurations available.

Current Applications

  • Matrix operations and product sum calculations
  • Wide word, high precision arithmetic processing
  • Fractal rendering and analysis at high magnification
  • RNS arithmetic algorithm development and analysis
  • Benchmarks coming soon!

NIOS and NIOS-II are registered trademarks of Altera Corporation.

*Rez-9 and its associated components are patent pending in the US and abroad.

Delivering the next leap in computation™